Alternative Processing Order with Efficient Architecture for Adaptive Deblocking Filter in H.264/avc

In this paper, we study and analyze the memory reference of deblocking filter in H.264/AVC baseline decoder based on SimpleScalar/ARM simulator. In order to reduce the number of memory references and thus improve overall system performance in an embedded system, we propose an advanced filtering process order with an efficient VLSI architecture which simultaneously processes the horizontal filtering of vertical edge and vertical filtering of horizontal edge. As a result, the performance of the proposed scheme is 129% faster than the advanced architecture of a previous proposal. Moreover, the number of the total memory references is reduced by 78.75% and 52.5% respectively compared to the basic and advanced architectures of the previous works.